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CppSim has served as a valuable tool in the development of new architectures for
custom integrated circuits. The publications listed here are the outcome of research
done at MIT in this area by Michael Perrott and his former students, and may be a
useful reference for those interested in the CppSim package. In particular, some of
the tutorials are based on work described in the publications listed here.
------------------------------------------------------------------------------------------------------------------
IEEE material is posted here with permission of the IEEE. Such permission of the IEEE does
not in any way imply IEEE endorsement of any of MIT's products or services. Internal or
personal use of this material is permitted. However, permission to reprint/republish this
material for advertising or promotional purposes or for creating new collective works for resale
or redistribution must be obtained from the IEEE by sending a blank email message to pubs-
permissions@ieee.org.
------------------------------------------------------------------------------------------------------------------
C.-M. Hsu, "Techniques for High-Performance Digital Frequency Synthesis and
Phase Control," PhD Thesis, MIT, September 2008. PDF
J. Kim, M.J. Park, M.H. Perrott, F.X. Kaertner, "Photonic subsampling analog-to-
digital conversion of microwave signals at 40-GHz with higher than 7-ENOB
resolution," Optics Express, Vol. 16, No. 21, 13 October 2008. PDF
M.Z. Straayer, M.H. Perrott, "An efficient high-resolution 11-bit noise-shaping
multipath gated ring oscillator TDC," IEEE VLSI Circuits Symp., Jun. 2008, pp. 82-83.
PDF
B.M. Helal, C.-M. Hsu, K. Johnson, M.H. Perrott, "A Low Noise Programmable Clock
Multiplier based on a Pulse Injection-Locked Oscillator with a Highly-Digital Tuning
Loop," Radio Frequency Integrated Circuits (RFIC) Symposium 2008, June 2008.
PDF
M.Z. Straayer, M.H. Perrott, "A 12-bit 10-MHz Bandwidth, Continuous-Time Sigma-
Delta ADC With a 5-Bit, 950-MS/S VCO-based Quantizer," IEEE J. Solid-State
Circuits, vol. 43, April 2008, pp. 805-814. PDF
B.M. Helal, M.Z. Straayer, M.H. Perrott, "A Highly Digital Clock Multiplier That
Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond
Jitter Performance," IEEE J. Solid-State Circuits, vol. 43, April 2008, pp. 855-863.
PDF
C.-M. Hsu, M.Z. Straayer, M.H. Perrott, "A Low-Noise, Wide-BW 3.6GHz Digital Delta-
Sigma Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital
Converter and Quantization Noise Cancellation," ISSCC 2008 Dig. Tech. Papers,
Feb. 2008, pp. 340-617. PDF
M.Z. Straayer, M.H. Perrott, "A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit
noise-shaping VCO-based Quantizer and DEM circuit in 0.13u CMOS," IEEE VLSI
Circuits Symp., Jun. 2007, pp. 246-247. PDF
B.M. Helal, M.Z. Straayer, G-Y Wei, M.H. Perrott, "A Low Jitter 1.6 GHz Multiplying
DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation," IEEE
VLSI Circuits Symp., Jun. 2007, pp. 166-167. PDF
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B.
Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25μm
CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter
and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits,
vol. 41, Dec. 2006, pp. 2930-2944. PDF
M. Park, J-W Kim, F. Kaetner, M.H. Perrott, "An Optical-Electrical Sub-Sampling
Receiver Employing Continuous-Time ΣΔ Modulation," ESSCIRC 2006 Dig. Tech.
Papers, Sep. 2006, pp. 182-185. PDF
C-M Hsu, C.Y. Lau, M.H. Perrott, "A Delay-Locked Loop using a Synthesizer-Based
Phase Shifter for 3.2 Gb/s Chip-to-Chip Communication," ESSCIRC 2006 Dig. Tech.
Papers, Sep. 2006, pp. 460-463. PDF
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, L. Zhang, J.P. Hein, "A 2.5 Gb/s
Multi-Rate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter," ISSCC
2006 Dig. Tech. Papers, Feb. 2006, pp. 1276-1285. PDF
S.E. Meninger, M.H. Perrott, "A 1-MHZ Bandwidth 3.6-GHz 0.18-um CMOS
Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced
Broadband Phase Noise," IEEE J. Solid-State Circuits, vol. 41, pp. 966-980, Apr.
2006. PDF
E.A. Crain, M.H. Perrott, "A 3.125 Gb/s Limit Amplifier in CMOS with 42 dB Gain and
1us Offset Compensation," IEEE J. Solid-State Circuits, vol. 41, pp. 443-451, Feb.
2006. PDF
S.E. Meninger, M.H. Perrott, "A Dual Band 1.8GHz/900MHz, 750kb/s GMSK
Transmitter Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase
Noise," IEEE VLSI Circuits Symp., Jun. 2005. PDF
S.E. Meninger, M.H. Perrott, "Bandwidth Extension of Low Noise Fractional-N
Synthesizers," Radio Frequency Integrated Circuits (RFIC) Symposium 2005, Jun.
2005. PDF
E. Crain, M. Perrott, "A 3.125Gb/s Limit Amplifier with 42dB Gain and 1μs Offset
Compensation in 0.18um CMOS," in ISSCC 2005 Dig. Tech. Papers, Feb. 2005, pp.
232-233, 595. PDF
J. Kim, F. X. Kärtner, M. H. Perrott, "Femtosecond synchronization of radio frequency
signals with optical pulse trains," Optics Letters, vol. 29, Issue 17, pp. 2076-2078,
Sep. 2004. PDF
E.A. Crain, M.H. Perrott, "A numerical Design Approach for High-Speed, Differential,
Resistor-Loaded, CMOS Amplifiers," IEEE International Symposium on Circuits and
Systems (ISCAS '04), May 2004. PDF
S.E. Meninger, M.H. Perrott, "A fractional- N frequency synthesizer architecture
utilizing a mismatch compensated PFD/DAC structure for reduced quantization-
induced phase noise," IEEE Trans. Circuits Syst. II, vol. 50, pp. 839-849, Nov. 2003.
PDF
C.Y. Lau, M.H. Perrott, "Phase Locked Loop Design at the Transfer Function Level
Based on a Direct Closed Loop Realization Algorithm", Design Automation
Conference (DAC), Jun. 2003, pp. 526-531. PDF
M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for Σ-Δ fractional-N
frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State
Circuits, vol. 37, pp. 1028-1038, Aug. 2002. PDF
M.H. Perrott, "Behavioral simulation of fractional-N frequency synthesizers and other
PLL circuits," IEEE Design & Test of Computers, vol. 19, pp. 74-83, Jul. 2002. PDF
M.H. Perrott, "Fast and Accurate Behavioral Simulation of Fractional-N Synthesizers
and other PLL/DLL Circuits", Design Automation Conference (DAC), Jun. 2002, pp
498-503. PDF
M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27-mW CMOS fractional-N synthesizer
using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State
Circuits, vol. 32, pp. 2048-2060, Dec. 1997. PDF
M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27mW CMOS fractional-N
synthesizer/modulator IC," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 366-
367, 487. PDF
custom integrated circuits. The publications listed here are the outcome of research
done at MIT in this area by Michael Perrott and his former students, and may be a
useful reference for those interested in the CppSim package. In particular, some of
the tutorials are based on work described in the publications listed here.
------------------------------------------------------------------------------------------------------------------
IEEE material is posted here with permission of the IEEE. Such permission of the IEEE does
not in any way imply IEEE endorsement of any of MIT's products or services. Internal or
personal use of this material is permitted. However, permission to reprint/republish this
material for advertising or promotional purposes or for creating new collective works for resale
or redistribution must be obtained from the IEEE by sending a blank email message to pubs-
permissions@ieee.org.
------------------------------------------------------------------------------------------------------------------
C.-M. Hsu, "Techniques for High-Performance Digital Frequency Synthesis and
Phase Control," PhD Thesis, MIT, September 2008. PDF
J. Kim, M.J. Park, M.H. Perrott, F.X. Kaertner, "Photonic subsampling analog-to-
digital conversion of microwave signals at 40-GHz with higher than 7-ENOB
resolution," Optics Express, Vol. 16, No. 21, 13 October 2008. PDF
M.Z. Straayer, M.H. Perrott, "An efficient high-resolution 11-bit noise-shaping
multipath gated ring oscillator TDC," IEEE VLSI Circuits Symp., Jun. 2008, pp. 82-83.
B.M. Helal, C.-M. Hsu, K. Johnson, M.H. Perrott, "A Low Noise Programmable Clock
Multiplier based on a Pulse Injection-Locked Oscillator with a Highly-Digital Tuning
Loop," Radio Frequency Integrated Circuits (RFIC) Symposium 2008, June 2008.
M.Z. Straayer, M.H. Perrott, "A 12-bit 10-MHz Bandwidth, Continuous-Time Sigma-
Delta ADC With a 5-Bit, 950-MS/S VCO-based Quantizer," IEEE J. Solid-State
Circuits, vol. 43, April 2008, pp. 805-814. PDF
B.M. Helal, M.Z. Straayer, M.H. Perrott, "A Highly Digital Clock Multiplier That
Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond
Jitter Performance," IEEE J. Solid-State Circuits, vol. 43, April 2008, pp. 855-863.
C.-M. Hsu, M.Z. Straayer, M.H. Perrott, "A Low-Noise, Wide-BW 3.6GHz Digital Delta-
Sigma Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital
Converter and Quantization Noise Cancellation," ISSCC 2008 Dig. Tech. Papers,
Feb. 2008, pp. 340-617. PDF
M.Z. Straayer, M.H. Perrott, "A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit
noise-shaping VCO-based Quantizer and DEM circuit in 0.13u CMOS," IEEE VLSI
Circuits Symp., Jun. 2007, pp. 246-247. PDF
B.M. Helal, M.Z. Straayer, G-Y Wei, M.H. Perrott, "A Low Jitter 1.6 GHz Multiplying
DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation," IEEE
VLSI Circuits Symp., Jun. 2007, pp. 166-167. PDF
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B.
Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25μm
CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter
and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits,
vol. 41, Dec. 2006, pp. 2930-2944. PDF
M. Park, J-W Kim, F. Kaetner, M.H. Perrott, "An Optical-Electrical Sub-Sampling
Receiver Employing Continuous-Time ΣΔ Modulation," ESSCIRC 2006 Dig. Tech.
Papers, Sep. 2006, pp. 182-185. PDF
C-M Hsu, C.Y. Lau, M.H. Perrott, "A Delay-Locked Loop using a Synthesizer-Based
Phase Shifter for 3.2 Gb/s Chip-to-Chip Communication," ESSCIRC 2006 Dig. Tech.
Papers, Sep. 2006, pp. 460-463. PDF
M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, L. Zhang, J.P. Hein, "A 2.5 Gb/s
Multi-Rate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter," ISSCC
2006 Dig. Tech. Papers, Feb. 2006, pp. 1276-1285. PDF
S.E. Meninger, M.H. Perrott, "A 1-MHZ Bandwidth 3.6-GHz 0.18-um CMOS
Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced
Broadband Phase Noise," IEEE J. Solid-State Circuits, vol. 41, pp. 966-980, Apr.
2006. PDF
E.A. Crain, M.H. Perrott, "A 3.125 Gb/s Limit Amplifier in CMOS with 42 dB Gain and
1us Offset Compensation," IEEE J. Solid-State Circuits, vol. 41, pp. 443-451, Feb.
2006. PDF
S.E. Meninger, M.H. Perrott, "A Dual Band 1.8GHz/900MHz, 750kb/s GMSK
Transmitter Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase
Noise," IEEE VLSI Circuits Symp., Jun. 2005. PDF
S.E. Meninger, M.H. Perrott, "Bandwidth Extension of Low Noise Fractional-N
Synthesizers," Radio Frequency Integrated Circuits (RFIC) Symposium 2005, Jun.
2005. PDF
E. Crain, M. Perrott, "A 3.125Gb/s Limit Amplifier with 42dB Gain and 1μs Offset
Compensation in 0.18um CMOS," in ISSCC 2005 Dig. Tech. Papers, Feb. 2005, pp.
232-233, 595. PDF
J. Kim, F. X. Kärtner, M. H. Perrott, "Femtosecond synchronization of radio frequency
signals with optical pulse trains," Optics Letters, vol. 29, Issue 17, pp. 2076-2078,
Sep. 2004. PDF
E.A. Crain, M.H. Perrott, "A numerical Design Approach for High-Speed, Differential,
Resistor-Loaded, CMOS Amplifiers," IEEE International Symposium on Circuits and
Systems (ISCAS '04), May 2004. PDF
S.E. Meninger, M.H. Perrott, "A fractional- N frequency synthesizer architecture
utilizing a mismatch compensated PFD/DAC structure for reduced quantization-
induced phase noise," IEEE Trans. Circuits Syst. II, vol. 50, pp. 839-849, Nov. 2003.
C.Y. Lau, M.H. Perrott, "Phase Locked Loop Design at the Transfer Function Level
Based on a Direct Closed Loop Realization Algorithm", Design Automation
Conference (DAC), Jun. 2003, pp. 526-531. PDF
M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for Σ-Δ fractional-N
frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State
Circuits, vol. 37, pp. 1028-1038, Aug. 2002. PDF
M.H. Perrott, "Behavioral simulation of fractional-N frequency synthesizers and other
PLL circuits," IEEE Design & Test of Computers, vol. 19, pp. 74-83, Jul. 2002. PDF
M.H. Perrott, "Fast and Accurate Behavioral Simulation of Fractional-N Synthesizers
and other PLL/DLL Circuits", Design Automation Conference (DAC), Jun. 2002, pp
498-503. PDF
M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27-mW CMOS fractional-N synthesizer
using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State
Circuits, vol. 32, pp. 2048-2060, Dec. 1997. PDF
M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27mW CMOS fractional-N
synthesizer/modulator IC," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 366-
367, 487. PDF
