CppSim automatically generates, compiles, and runs C++ code corresponding to the schematic design that you create.
Systems are specified and simulated within a schematic editor, Sue2, and results are viewed using a waveform viewer (CppSimView or GTKWave).
A simple text template for each module is filled in by the user which can make use of a rich set of C++ classes to represent common functions such as filtering, noise, etc.
CppSim utilizes Verilator to automatically create C++ code corresonding to your Verilog modules, and seamlessly integrates this code into your system simulation.
Linear networks and switches:
CppSim automatically creates a C++ state-space representation of linear networks with switches in your schematic design, and seamlessly includes this code in the simulation.
VppSim combines Verilog with CppSim to seamlessly include C++ modules and linear networks with switches with Verilog as specified within a schematic driven framework.
NGspice is included as a standalone tool for transistor level simulations and utilizes the schematic editor and waveform viewer of the CppSim framework.
Postprocessing with Python, Matlab®, and Octave
CppSim simulations are easily read into Python, Matlab®, and Octave to allow seamless postprocessing of your results.
Click the Download button to install, and start with the CppSim Primer in the Manuals section to learn how to use the tool.